LTC3721EUF-1 [Linear Systems]
Push-Pull PWM Controller; 推挽式PWM控制器
| 型号： | LTC3721EUF-1 |
| 厂家： | 
Linear Systems |
| 描述： | Push-Pull PWM Controller |
| 文件： | 总16页 (文件大小：181K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC3721-1
Push-Pull PWM Controller
U
DESCRIPTIO
FEATURES
The LTC®3721-1 push-pull PWM controller provides all of
the control and protection functions necessary for com-
pact and highly efficient, isolated power converters. High
integration minimizes external component count, while
preserving design flexibility.
■
High Efficiency Push-Pull PWM
■
1.5A Sink, 1A Source Output Drivers
■
Adjustable Push-Pull Dead-Time
■
Adjustable System Undervoltage Lockout and
Hysteresis
■
Adjustable Leading Edge Blanking
The robust push-pull output stages switch at half the
oscillator frequency. Dead-time is independently pro-
grammedwithanexternalresistor. AUVLOprograminput
providesprecisesystemturn-onandturnoffvoltages.The
LTC3721-1 features peak current mode control with pro-
grammable slope compensation and leading edge
blanking.
■
Low Start-Up and Quiescent Currents
■
Current Mode Operation
■
Single Resistor Slope Compensation
■
VCC UVLO and 25mA Shunt Regulator
■
Programmable Fixed Frequency Operation to 1MHz
■
Soft-Start, Cycle-by-Cycle Current Limiting and
Hiccup Mode Short-Circuit Protection
5V, 15mA Low Dropout Regulator
■
■
The LTC3721-1 features extremely low operating and
start-up currents and reliable short-circuit and
overtemperature protection. The LTC3721-1 is offered in
16-pin SSOP and (4mm × 4mm) QFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
16-Pin SSOP and (4mm × 4mm) QFN Packages
U
APPLICATIO S
■
Telecommunications, Infrastructure Power Systems
■
Distributed Power Architectures
■
Server Power Supplies
High Density Power Modules
■
U
TYPICAL APPLICATIO
Isolated Push-Pull Converter
V
V
IN
OUT
+
UVLO
DRVA
FROM
AUXILIARY
WINDING
DRVB
CS
V
CC
DPRG
LTC3721-1
R
CS
V
REF
C
T
V
REF
R
LEB
V
OUT
V
OUT
SS
COMP
+
V
R
TOP
COLL
R
REF
LT1431
GND-F GND-S
FB GND
COMP
R
MID
37211 TA01
sn37211 37211fs
1
LTC3721-1
W W
U W
ABSOLUTE AXI U RATI GS
(Note 1)
VCC to GND (Low Impedance Source) .......–0.3V to 10V
(Chip Self-Regulates at 10.3V)
UVLO to GND............................................. –0.3V to VCC
All Other Pins to GND
(Low Impedance Source) .........................–0.3V to 5.5V
VCC (Current Fed) ................................................. 40mA
VREF Output Current ............................... Self-Regulated
Operating Temperature (Notes 5,6)
LTC3721-1 ......................................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (GN Package only)
(Soldering, 10sec) ............................................ 300°C
U
W
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
ORDER PART
ORDER PART
TOP VIEW
V
1
2
3
4
5
6
7
8
16 NC
15 UVLO
14 SS
13 FB
NUMBER
NUMBER
REF
NC
16 15 14 13
LTC3721EGN-1
LTC3721EUF-1
NC
DRVB
1
2
3
4
12 FB
DRVB
V
11
10
9
R
LEB
CC
17
V
12 R
LEB
DRVA
PGND
COMP
CS
CC
DRVA
GND
11 COMP
10 CS
GN PART
MARKING
UF PART
MARKING
5
6
7
8
C
T
9
DPRG
37211
UF PACKAGE
16-LEAD (4mm × 4mm) PLASTIC QFN
37211
GN PACKAGE
16-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 100°C/W
TJMAX = 125°C, θJA = 100°C/W
EXPOSED PAD IS GND
(PIN17) MUST BE SOLDERED TO PCB
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply
V
V
V
V
Undervoltage Lockout
UVLO Hysteresis
Measured on V
Measured on V
10.25
4.2
145
3
10.7
V
V
CCUV
CCHY
CCST
CCRN
CC
CC
CC
3.8
CC
I
I
Start-Up Current
V
= V
– 0.3V
UVLO
●
230
6
µA
mA
V
CC
Operating Current
No Load on Outputs
Current into V = 10mA
V
Shunt Regulator Voltage
Shunt Resistance
10.3
1.4
5.0
10
10.8
3.5
5.2
11.5
SHUNT
CC
R
Current into V = 10mA to 17mA
Ω
SHUNT
CC
SUVLO
SHYST
System UVLO Threshold
System UVLO Hysteresis Current
Measured on UVLO Pin, 10mA into V
4.8
8.5
V
CC
Current Flows Out of UVLO Pin, 10mA into V
µA
CC
sn37211 37211fs
2
LTC3721-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
Pulse Width Modulator
ROS Ramp Offset Voltage
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Measured on COMP, CS = 0V
0.65
50
V
I
I
Ramp Discharge Current
CS = 1V, COMP = 0V, C = 4V
mA
RMP
SLP
T
Slope Compensation Current
Measured on CS, C = 1V
30
68
µA
µA
T
C = 2.25V
T
DCMAX
DCMIN
DTADJ
Oscillator
OSCI
Maximum Duty Cycle
Minimum Duty Cycle
Dead-Time
COMP = 4.5V
COMP = 0V
●
●
47
48.2
0
50
%
%
ns
130
Initial Accuracy
T = 25°C, C = 270pF
220
–3
250
2.35
1.2
280
3
kHz
%
A
T
OSCT
V
Variation
V
= 6.5V to 9.5V
CC
●
CC
OSCV
C Ramp Amplitude
T
Measured on C
V
T
Error Amplifier
V
FB Input Voltage
FB Input Range
Open-Loop Gain
Input Bias Current
Output High
COMP = 2.5V, (Note 3)
Measured on FB, (Note 4)
COMP = 1V to 3V, (Note 3)
COMP = 2.5V, (Note 3)
Load on COMP = –100µA
Load on COMP = 100µA
COMP = 2.5V
1.172
–0.3
70
1.22
2.5
V
V
FB
FB
I
AVOL
90
5
dB
nA
V
I
50
IB
V
V
4.7
4.92
0.27
700
5
OH
Output Low
0.5
V
OL
I
I
Output Source Current
Output Sink Current
400
2
µA
mA
SOURCE
SINK
COMP = 2.5V
Reference
V
Initial Accuracy
Load Regulation
Line Regulation
Total Variation
T = 25°C, Measured on V
REF
4.925
5.00
2
5.075
15
V
mV
mV
V
REF
A
REFLD
REFLN
REFTV
REFSC
Load on V = 100µA to 5mA
REF
V
= 6.5V to 9.5V
1
10
CC
Line, Load and Temperature
●
4.900
18
5.000
30
5.100
45
Short-Circuit Current
V
Shorted to GND
mA
REF
Push-Pull Outputs
DRVH(x)
DRVL(x)
RDH(x)
RDL(x)
TDR(x)
TDF(x)
Output High Voltage
I
I
I
I
= –100mA
9.2
0.17
2.9
1.7
10
V
V
OUT(x)
OUT(x)
OUT(x)
OUT(x)
Output Low Voltage
Pull-Up Resistance
Pull-Down Resistance
Rise-Time
= 100mA
= –10mA to –100mA
= –10mA to –100mA
= 1nF
Ω
Ω
ns
ns
C
C
OUT(x)
OUT(x)
Fall-Time
= 1nF
10
Current Limit and Shutdown
CLPP
CLSD
CLDEL
SSI
Pulse by Pulse Current Limit Threshold
Measured on CS
280
475
300
600
80
320
725
mV
mV
ns
Shutdown Current Limit Threshold
Current Limit Delay to Output
Soft-Start Current
Measured on CS
100mV Overdrive on CS, (Note 2)
SS = 2.5V
10
13
16
µA
sn37211 37211fs
3
LTC3721-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 9.5V unless otherwise noted.
SYMBOL
SSR
PARAMETER
CONDITIONS
Measured on SS
Measured on SS
MIN
0.7
TYP
0.4
4.2
MAX
0.1
UNITS
Soft-Start Reset Threshold
Fault Reset Threshold
V
V
FLT
4.5
3.5
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 5: The LTC3721–1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 2: Includes leading edge blanking delay, R = 20k, not tested in
LEB
production.
Note 6: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: FB is driven by a servo loop amplifier to control V
tests.
Note 4: Set FB to –0.3V, 2.5V and insure that COMP does not phase invert.
for these
COMP
U W
(TA = 25°C unless otherwise noted)
TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency vs
Temperature
Start-Up ICC vs VCC
VCC vs ISHUNT
10.50
10.25
10.00
9.75
200
150
100
50
260
250
240
230
220
C
= 270pF
T
9.50
0
0
10
20
30
40
50
0
2
4
6
8
10
–60 –40 –20
0
20 40 60 80 100
I
(mA)
V
(V)
TEMPERATURE (°C)
SHUNT
CC
372311 G02
372311 G01
372311 G03
Leading Edge Blanking Time
vs RLEB
VREF vs Temperature
VREF vs IREF
5.01
5.00
4.99
4.98
4.97
350
300
250
200
150
100
50
5.05
5.00
4.95
4.90
4.85
4.80
T
= 25°C
J
T
= 85°C
J
T
= –40°C
J
0
–60 –40 –20
0
20 40 60 80 100
20
(mA)
5
10 15
25 30 35 40
0
0
10 20 30 40 50
70
90 100
80
60
TEMPERATURE (°C)
R
(kΩ)
I
LEB
REF
372311 G06
372311 G05
372311 G04
sn37211 37211fs
4
LTC3721-1
U W
TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25°C unless otherwise noted)
Error Amplifier Gain/Phase
Deadtime vs RDPRG
Start-Up ICC vs Temperature
275
250
225
200
175
150
125
100
75
190
180
170
160
150
140
130
120
110
100
100
80
60
40
20
0
200k PREBIAS
NO 200k PREBIAS
–180
–270
–360
50
10
100
1k
10k
100k 1M
10M
0
100 150 200 250 300 350 400 450 500
50
–55
–25
5
35
65
95
125
FREQUENCY (Hz)
R
(kΩ)
TEMPERATURE (°C)
DPRG
372311 G07
372311 G09
372311 G08
V
CC Shunt Voltage vs
Slope Current vs Temperature
Temperature
FB Input Voltage vs Temperature
10.5
10.4
10.3
10.2
10.1
10.0
9.9
1.205
1.204
1.203
1.202
1.201
1.200
1.199
1.198
1.197
90
80
70
60
50
40
30
20
10
0
I
= 10mA
CC
C
= 2.25V
T
C
= 1V
T
9.8
–55
–25
5
35
65
95
125
–55
–25
5
35
65
95
125
–55
–25
5
35
65
95
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
372311 G11
372311 G12
372311 G10
sn37211 37211fs
5
LTC3721-1
U
U
PI DESCRIPTIO S
(GN Package/UF Package)
VREF (Pin 1/Pin 15): Output of the 5.0V Reference. VREF is
capableofsupplyingupto18mAtoexternalcircuitry.VREF
shouldbedecoupledtoGNDwitha1µFceramiccapacitor.
GND as practical for best performance. For the 4mm ×
4mm QFN package only, the internal power (PGND) and
signal (SGND) buses are connected separately to pins 4
and 5 respectively, and the exposed pad must be soldered
to PCB ground.
DRVB (Pin 4/Pin 1): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
CT (Pin 8/Pin 6): Timing Capacitor for the Oscillator. Use
a ±5% or better low ESR ceramic capacitor for best
results. CT ramp amplitude is 2.35V peak-to-peak
(typical).
DPRG (Pin 9/Pin 8): Programming Input for Push-Pull
Dead-Time. Connect a resistor between DPRG and VREF to
program the dead-time. The nominal voltage on DPRG is
2V.
V
CC (Pin 5/Pin 2): Supply Voltage Input to the LTC3721-1
and 10.25V Shunt Regulator. The chip is enabled after VCC
has risen high enough to allow the VCC shunt regulator to
conduct current and the UVLO comparator threshold is
exceeded. Once the VCC shunt regulator has turned on,
VCC can drop to as low as 6V (typical) and maintain
operation. Bypass VCC to GND with a high quality 1µF or
larger ceramic capacitor to supply the transient currents
caused by the high speed switching and capacitive loads
presented by the on chip totem pole drivers.
CS (Pin 10/Pin 9): Input to Pulse-by-Pulse and Overload
Current Limit Comparators, Output of Slope Compensa-
tionCircuitry. Thepulse-by-pulsecomparatorhasanomi-
nal 300mV threshold, while the overload comparator has
anominal600mVthreshold.Aninternalswitchdischarges
CS to GND after every timing period. Slope compensation
current flows out of CS during the PWM period.
An external resistor connected from CS to the external
current sense resistor programs the amount of slope
compensation.
DRVA (Pin 6/Pin 3): High Speed 1.5A Sink, 1A Source
Totem Pole MOSFET Driver. Connect to gate of external
push-pull MOSFET with as short a PCB trace as practical
to preserve drive signal integrity. A low value resistor
connected between DRVA and the MOSFET gate is op-
tional and will improve the gate drive signal quality if the
PCB trace from the driver to the MOSFET cannot be made
short.
COMP (Pin 11/Pin 10): Error Amplifier Output, Inverting
Input to Phase Modulator.
RLEB (Pin 12/Pin 11): Timing Resistor for Leading Edge
Blanking. Use a 10k to 100k resistor connected between
RLEB and GND to program from 40ns to 310ns of leading
edge blanking of the current sense signal on CS for the
LTC3721-1. A ±1% tolerance resistor is recommended.
The nominal voltage on RLEB is 2V. If leading edge blank-
ing is not required, tie RLEB to VREF to disable.
GND (Pin 7/Pin 4, Pin 5, Pin 17): All circuits in the
LTC3721-1 are referenced to GND. Use of a ground plane
is highly recommended. VIN and VREF bypass capacitors
must be terminated with a star configuration as close to
sn37211 37211fs
6
LTC3721-1
U
U
PI DESCRIPTIO S
(GN Package/UF Package)
FB (Pin 13/Pin 12): Error Amplifier Inverting Input. This is
the voltage feedback input for the LTC3721-1. The nomi-
nal regulation voltage at FB is 1.2V.
UVLO (Pin 15/Pin 14): Input to Program System Turn-On
andTurn-OffVoltages.ThenominalthresholdoftheUVLO
comparator is 5.0V. UVLO is connected to the main DC
system feed through a resistor divider. When the UVLO
threshold is exceeded, the LTC3721-1 commences a soft-
startcycleanda10µA(nominal)currentisfedoutofUVLO
to program the desired amount of system hysteresis. The
hysteresis level can be adjusted by changing the resis-
tance of the divider. UVLO can also be used to terminate
all switching by pulling UVLO down to less than 4V. An
open drain or collector switch can perform this function
without changing the system turn on or turn off voltages.
SS (Pin 14/Pin 13): Soft-Start/Restart Delay Circuitry
Timing Capacitor. A capacitor from SS to GND provides a
controlledrampofthecurrentcommand. Duringoverload
conditions, SS is discharged to ground initiating a soft-
startcycle.SSchargingcurrentisapproximately13µA.SS
will charge up to approximately 5V in normal operation.
During a constant overload current fault, SS will oscillate
at a low frequency between approximately 0.5V and 4V.
NC (Pin 2, Pin 3, Pin 16/Pin 7, Pin 16): Not Connected.
W U
TI I G DIAGRA
W
PROGRAMMABLE
DEAD-TIME
DRVA
DRVB
CURRENT
SENSE
OR C RAMP
T
PWM
COMPARATOR
(–)
37211 TD01
sn37211 37211fs
7
LTC3721-1
W
BLOCK DIAGRA S
sn37211 37211fs
8
LTC3721-1
U
OPERATIO
Please refer to the detailed Block Diagram for this discus-
sion. The LTC3721-1 is a PWM push-pull controller that
operates with pulse-by-pulse peak current mode control.
It is best suited for moderate to high power isolated power
systems where small size and high efficiency are required.
The push-pull topology delivers excellent transformer
utilization and requires only two low side power MOSFET
switches. The controller generates 180° out of phase
0% to <50% duty cycle drive signals on DRVA and DRVB.
The external MOSFETs are driven directly by these power-
ful on-chip drivers. The external MOSFETs typically con-
trol opposite primary windings of a centertapped power
transformer. The centertap primary winding is connected
totheinputDCfeed. Thesecondaryofthetransformercan
beconfiguredindifferentsynchronousornonsynchronous
configurations depending on the application needs.
sets a maximum deadtime if DPRG is floated. The internal
current source causes the programmed deadtime to vary
non-linearly with increasing values of RDPRG (see Typical
Performance Characteristics). An external 200k resistor
connected from DPRG to GND will compensate for the
internal 10µA current source and linearize the deadtime
delay vs RDPRG characteristic.
V
REF
R
DPRG
DPRG
OPTIONAL
+
–
+
V
–
TURN-ON
OUTPUT
200k
2V
2.5V
37211 F01
Figure 1. Deadtime Adjust
The duty ratio is controlled by the voltage on COMP. A
switching cycle commences with the falling edge of the
internal oscillator clock pulse. The LTC3721-1 attenuates
the voltage on COMP and compares it to the current sense
signaltoterminatetheswitchingcycle.IfthevoltageonCS
exceeds 300mV, the present cycle is terminated. If the
voltage on CS exceeds 600mV, all switching stops and a
soft-start sequence is initiated.
Powering the LTC3721-1
The LTC3721-1 utilizes an integrated VCC shunt regulator
to serve the dual purposes of limiting the voltage applied
to VCC as well as signaling that the chip’s bias voltage is
sufficient to begin switching operation (under voltage
lockout). With its typical 10.2V turn-on voltage and 4.2V
UVLO hysteresis, the LTC3721-1 is tolerant of loosely
regulated input sources such as an auxiliary transformer
winding. The VCC shunt is capable of sinking up to 40mA
of externally applied current. The UVLO turn-on and turn-
off thresholds are derived from an internally trimmed
reference making them extremely accurate. In addition,
the LTC3721-1 exhibits very low (145µA typ) start-up
current that allows the use of 1/8W to 1/4W trickle charge
start-up resistors.
A host of other features including an error amplifier,
systemUVLOprogramming,adjustableleadingedgeblank-
ing, slope compensation and programmable dead-time
provide flexibility for a variety of applications.
Programming Driver Dead-Time
The LTC3721-1 includes a feature to program the mini-
mum time between the output signals on DRVA and DRVB
commonly referred to as the driver dead-time. This func-
tion will come into play if the controller is commanded for
maximum duty cycle. The dead-time is set with an
external resistor connected between DPRG and VREF (see
Figure 1). The nominal regulated voltage on DPRG is 2V.
The external resistor programs a current which flows into
DPRG. The dead-time can be adjusted from 90ns to 300ns
with this resistor. The dead-time can also be modulated
basedonanexternalcurrentsourcethatfeedscurrentinto
DPRG. Care must be taken to limit the current fed into
DPRG to 350µA or less. An internal 10µA current source
The trickle charge resistor should be selected as follows:
RSTART(MAX) = VIN(MIN) – 10.7V/250µA
Adding a small safety margin and choosing standard
values yields:
APPLICATION
DC/DC
V
RANGE
R
START
IN
36V to 72V
85V to 270V
100k
430k
1.4M
Off-Line
RMS
PFC Preregulator
390V
DC
sn37211 37211fs
9
LTC3721-1
U
OPERATIO
UVLOispresentandgreaterthan5VpriortotheVCC UVLO
circuitry activation, then the internal UVLO logic will
prevent output switching until the following three condi-
tions are met: (1) VCC UVLO is enabled, (2) VREF is in
regulation and (3) UVLO pin is greater than 5V.
VCC should be bypassed with a 0.1µF to 1µF multilayer
ceramic capacitor to decouple the fast transient currents
demanded by the output drivers and a bulk tantalum or
electrolytic capacitor to hold up the VCC supply before the
bootstrap winding, or an auxiliary regulator circuit takes
over.
UVLO can also be used to enable and disable the power
converter. An open drain transistor connected to UVLO as
shown in Figure 3 provides this capability.
C
HOLDUP = (ICC + IDRIVE) • tDELAY/3.8V
(minimum UVLO hysteresis)
Regulated bias supplies as low as 7V can be utilized to
provide bias to the LTC3721-1. Refer to Figure 2 for
various bias supply configurations.
Off-Line Bias Supply Generation
If a regulated bias supply is not available to provide VCC
voltage to the LTC3721-1 and supporting circuitry, one
must be generated. Since the power requirement is small,
approximately 1W, and the regulation is not critical, a
simpleopen-loopmethodisusuallytheeasiestandlowest
cost approach. One method that works well is to add a
winding to the main power transformer, and post regulate
theresultantsquarewavewithanL-Cfilter(seeFigure 4a).
The advantage of this approach is that it maintains decent
regulation as the supply voltage varies, and it does not
require full safety isolation from the input winding of the
transformer.Somemanufacturersincludeaprimarywind-
ing for this purpose in their standard product offerings as
well. A different approach is to add a winding to the output
inductor and peak detect and filter the square wave signal
(see Figure 4b). The polarity of this winding is designed so
Programming Undervoltage Lockout
The LTC3721-1 provides undervoltage lockout (UVLO)
control for the input DC voltage feed to the power con-
verterinadditiontotheVCCUVLOfunctiondescribedinthe
preceding section. Input DC feed UVLO is provided with
the UVLO pin. A comparator on UVLO compares a divided
down input DC feed voltage to the 5V precision reference.
When the 5V level is exceeded on UVLO, the SS pin is
released and output switching commences. At the same
time a 10µA current is enabled which flows out of UVLO
intothevoltagedividerconnectedtoUVLO. Theamountof
DC feed hysteresis provided by this current is: 10µA •
RTOP, (Figure 3). The system UVLO threshold is: 5V •
{(RTOP + RBOTTOM)/RBOTTOM}. If the voltage applied to
V
IN
V
CC
V
IN
V
BIAS
< V
UVLO
12V ±10%
1.5k
R
START
1N5226
3V
1N914
R
START
2k
+
15V*
1µF
C
HOLD
+
1µF
1µF
C
HOLD
19211 F04a
V
CC
V
CC
37211 F02
*OPTIONAL
Figure 4a. Auxiliary Winding Bias Supply
Figure 2. Bias Configurations
V
IN
V
OUT
L
OUT
R
TOP
R
START
+
ISO BARRIER
UVLO
1µF
C
HOLD
ON OFF
R
BOTTOM
19211 F04b
37211 F03
V
CC
Figure 4b. Output Inductor Bias Supply
Figure 3. System UVLO Setup
sn37211 37211fs
10
LTC3721-1
U
OPERATIO
thatthepositivevoltagesquarewaveisproducedwhilethe
output inductor is freewheeling. An advantage of this
technique over the previous is that it does not require a
separate filter inductor and since the voltage is derived
from the well-regulated output voltage, it is also well
controlled. One disadvantage is that this winding will
require the same safety isolation that is required for the
main transformer. Another disadvantage is that a much
larger VCC filter capacitor is needed, since it does not
generate a voltage as the output is first starting up, or
during short-circuit conditions.
Current Sensing and Overcurrent Protection
Current sensing provides feedback for the current mode
control loop and protection from overload conditions. The
LTC3721-1 is compatible with either resistive sensing or
current transformer methods. Internally connected to CS
are two comparators that provide pulse-by-pulse and
overcurrent shutdown functions respectively, (Figure 6).
The pulse-by-pulse comparator has a 300mV nominal
threshold. If the 300mV threshold is exceeded, the PWM
cycle is terminated. The overcurrent comparator is set
approximately 2x higher than the pulse-by-pulse level. If
the current signal exceeds this level, the PWM cycle is
terminated, the soft-start capacitor is quickly discharged
and a soft-start cycle is initiated. If the overcurrent condi-
tion persists, the LTC3721-1 halts PWM operation and
waits for the soft-start capacitor to charge up to approxi-
mately 4V before a retry is allowed. The soft-start capaci-
tor is charged by an internal 13µA current source. If the
faultconditionhasnotclearedwhensoft-startreaches4V,
the soft-start pin is again discharged and a new cycle is
initiated. This is referred to as hiccup mode operation. In
normal operation and under most abnormal conditions,
the pulse-by-pulse comparator is fast enough to prevent
hiccup mode operation. In severe cases, however, with
high input voltage, very low RDS(ON) MOSFETs and a
shorted output, or with saturating magnetics, the
overcurrent comparator provides a means of protecting
the power converter.
Programming the LTC3721-1 Oscillator
The high accuracy LTC3721-1 oscillator circuit provides
flexibility to program the switching frequency and slope
compensation required for current mode control. The
oscillator circuit produces a 2.35V peak-to-peak ampli-
tude ramp waveform on CT. Typical maximum duty cycles
of 49% are possible. The oscillator is capable of operation
up to 1MHz by the following equation:
CT = 1/(14.8k • FOSC
)
Note that this is the frequency seen on CT. The output
drivers switch at 1/2 of this frequency. Also note that
higher switching frequency and added driver dead-time
via DPRG will reduce the maximum duty cycle.
The LTC3721-1 derives a compensating slope current
from the oscillator ramp waveform and sources this
currentoutofCS. Thedesiredlevelofslopecompensation
isselectedwithanexternalresistorconnectedbetweenCS
and the external current sense resistor, (Figure 5).
H = SHUTDOWN
PWM
OUTPUTS
UVLO
ENABLE
LATCH
PULSE BY PULSE
CURRENT LIMIT
PWM
LOGIC
Q
Q
PWM
+
S
R
Q
S
CS
CS
–
300mV
OVERLOAD
CURRENT LIMIT
R
+
–
+
13µA
4.1V
0.4V
LTC3721-1
SWITCH
S
R
Q
–
650mV
SS
V(C )
T
33k
CURRENT
I =
UVLO
ENABLE
R
SLOPE
C
+
–
T
CS
C
SS
ADDED
SLOPE
R
CS
33k
Q
CURRENT SENSE
WAVEFORM
37211 F06
37211 F05
Figure 5. Slope Compensation Circuitry
Figure 6. Current Sense/Fault Circuitry Detail
sn37211 37211fs
11
LTC3721-1
U
OPERATIO
Leading Edge Blanking
is highly recommended. The driver output pins (DRVA,
DRVB) connect to the gates of the external MOSFET
switches.ThePCBtracesmakingtheseconnectionsshould
also be as short as possible to minimize overshoot and
undershoot of the drive signal.
The LTC3721-1 provides programmable leading edge
blanking to prevent nuisance tripping of the current sense
circuitry. Leading edge blanking relieves the filtering re-
quirements for the CS pin, greatly improving the response
to real overcurrent conditions. It also allows the use of a
groundreferencedcurrentsenseresistorortransformer(s),
further simplifying the design. With a single 10k to 100k
resistor from RLEB to GND, blanking times of approxi-
mately 40ns to 320ns are programmed. If not required,
connecting RLEB to VREF can disable leading edge blank-
ing. Keep in mind that the use of leading edge blanking will
slightly reduce the linear control range for the pulse width
modulator.
Transformer Configurations
The LTC3721-1 used in a typical isolated push-pull con-
verter application will need a transformer to provide the
voltage translation and galvanic isolation. The push-pull
transformer employs a center tapped primary winding
configuration. The transformer secondary can be center
tappedorasinglewindingdependingontheconfiguration
and application needs.
Center tapped secondary configurations apply alternating
<50% duty cycle square waves to a single inductor/
capacitor combination. This L-C circuit filters the square
wave and produces the regulated output voltage. The
secondary square wave amplitude is given by:
High Current Drivers
The LTC3721-1 high current, high speed drivers provide
directdriveofexternalpowerN-channelMOSFETswitches.
The drivers swing from rail to rail. Due to the high pulsed
currentnatureofthesedrivers(1.5Asink,1Asource),care
must be taken with the board layout to obtain advertised
performance. Bypass VCC with a 1µF minimum, low ESR,
ESL ceramic capacitor. Connect this capacitor with mini-
mallengthPCBleadstobothVCC andGND.Agroundplane
VSEC = VIN • N, where N = Ns/Np, transformer turns
ratio, # of secondary turns divided by # of primary
turns.
sn37211 37211fs
12
LTC3721-1
U
OPERATIO
The duty cycle of these square waves is guaranteed to
never exceed 50% by the LTC3721-1. In steady state
operation, the duty ratio is given by:
Note that this is a simplified equation that does not take
into account primary and secondary side voltage drops
due to diodes, power MOSFETs, and resistive elements in
thepowerpaths. BymarginingdownVIN(MIN) andDMAX as
suggested above, the equation becomes closer to reality.
D = VOUT/(2 • VIN • N)
To calculate the transformer turns ratio, first determine
the minimum input voltage (VIN(MIN)) and the maximum
duty ratio (D(MAX)) of the controller IC. This will be the
worst case condition. An example is provided below:
An alternative secondary winding configuration uses a
single non-center tapped winding and two filter inductors.
Each end of the secondary winding alternately drives an
inductor with <50% duty cycle square wave. The two
inductors are connected together at the opposite ends to
common output filter capacitor(s). This configuration is
also called the current doubler rectifier. The current dou-
bler utilizes half of the secondary windings compared to
the center tapped case. The two out of phase inductors
reduce the ripple current seen by the output and input
capacitors, possibly allowing fewer capacitors in some
applications. In addition, each output inductor carries half
of the total load current, making them physically smaller,
which can help to optimize the power stage layout. How-
ever, the total combined size may be slightly larger than
the single inductor configuration.
VIN = 32V to 75V, use VIN(MIN) = 30V to account for
system voltage drops.
V
OUT = 7V
Maximum duty cycle (DMAX) = 47% (per datasheet),
use 45% for margin.
The required transformer turns ratio is given by:
Turns ratio (Ns/Np) = VOUT/(VIN(MIN) • 2 • D(MAX)
= 7V/(30V • 2 • 0.45)
)
Ns/Np = (1/3.86)
sn37211 37211fs
13
LTC3721-1
U
PACKAGE DESCRIPTIO
GN Package
16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.189 – .196*
(4.801 – 4.978)
.045 ±.005
.009
(0.229)
REF
16 15 14 13 12 11 10 9
.254 MIN
.150 – .165
.229 – .244
.150 – .157**
(5.817 – 6.198)
(3.810 – 3.988)
.0165 ±.0015
.0250 BSC
RECOMMENDED SOLDER PAD LAYOUT
1
2
3
4
5
6
7
8
.015 ± .004
(0.38 ± 0.10)
× 45°
.0532 – .0688
(1.35 – 1.75)
.004 – .0098
(0.102 – 0.249)
.007 – .0098
(0.178 – 0.249)
0° – 8° TYP
.016 – .050
(0.406 – 1.270)
.0250
(0.635)
BSC
.008 – .012
GN16 (SSOP) 0204
(0.203 – 0.305)
TYP
NOTE:
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
sn37211 37211fs
14
LTC3721-1
U
PACKAGE DESCRIPTIO
UF Package
16-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1692)
0.72 ±0.05
4.35 ± 0.05
2.90 ± 0.05
2.15 ± 0.05
(4 SIDES)
PACKAGE OUTLINE
0.30 ±0.05
0.65 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
BOTTOM VIEW—EXPOSED PAD
0.75 ± 0.05
R = 0.115
TYP
0.55 ± 0.20
4.00 ± 0.10
(4 SIDES)
15
16
PIN 1
TOP MARK
(NOTE 6)
1
2
2.15 ± 0.10
(4-SIDES)
(UF) QFN 1103
0.30 ± 0.05
0.65 BSC
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
sn37211 37211fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC3721-1
U
TYPICAL APPLICATIO
180pF
200V
160Ω
2W
COEV MGPWG-00001
EFD25 (1.28" x 1" x 0.504")
+V
C8
S
4T (42µH) CT: 10T CT: 10T CT
(PINS 1 TO 6, 7 TO 9, 11 TO 12)
12
11
+V
OUT
•
•
+
C6
56µF
35V
MBRB20200CT
1
160Ω
C1
1µF
V
•
IN
2W
4
1
3
2
100V
3
+V
12V
–V
IN
IN
IN
4
6
0.1µF
L1
22µH
48V/3.65A
1nF
1nF
200V
C64
100V
+
C9
39µF
100V
200V
180pF
200V
5.1Ω
1/2W
5.1Ω
1/2W
C2, C3, C4, C5
4x33µF
10
9
16V
–V
OUT
T2
24V
0.59mH
PULSE
P0353
–V
S
•
•
2xSi7370DP
2xSi7370DP
+
MBRB20200CT
C7
56µF
35V
92
91
90
89
88
8
7
L2
22µH
10.6V
IN
R1
0.01Ω
1.5W
R2
0.01Ω
1.5W
13.2V
IN
1.21k
5V
12V
73.2k
IN
4.7Ω
1/4W
4.7Ω
1/4W
330pF
FMMT718
FMMT718
V
IN
470Ω
MMBT3904LT1
470Ω
107k
1.5k
1/4W
24V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
6
10
4
LOAD CURRENT (A)
+V
DRVA
CS
DRVB
S
5
V
CC
1k
NOTES:
T2, C1, C9 ARE OPTIONAL AND
REDUCE OUTPUT RIPPLE TO LESS
THAN 50mV
10mA MINIMUM LOAD REQUIRED.
START VOLTAGE 10.8V MAX.
2k
LTC3721EGN-1
1
15
11
MOC207
UVLO
C
COMP
46.1k
10k
.
P-P
10nF
3
R
LEB
GND FB SS DPRG
13 14
V
T
REF
6
8
12
7
9
1
1nF
100V
1nF
2
4
1.2k
C2-C5: TDK C4532X7R1336M (1812)
C10: MURATA DE2E3KH222MB3B
C1: TDK C3225X7R2A105M (1210)
C6, C7: SANYO 35MV56WX
+
COMP RTOP
LT1431CS8
COLL
V
10k
5
2
1
8
1µF
REF
D1
9.1V
D2
9.1V
C9: SANYO 100MV39AX
C10
2.2nF
250V
GND-F GND-S RMID
C8: TDK C3216X7R2A104M (X7R 1206)
D1, D2: MMBZ5239B
R1, R2: IRC LRC-LR2512-01-R010-G
L1, L2: TDK SLF12575T-220M4R0
2.49k
33k
270pF
68nF
1µF
1.5nF
100k
100k
6
5
7
–V
S
37211 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
Drives Opto-Coupler
LT1431
Reference and Opto-Driver
LT1681/LT3781
LTC1693-1
LT1950
Synchronous Forward Controllers
Dual MOSFET Gate Drivers
High Efficiency 2-Switch Forward Control
High Speed MOSFET Gate Drivers
Single Switch Forward Converter Controller
Auxillary Boost Converter, Programmable Volt-SPC Clamp
ZVS Full-Bridge Controllers
LTC3722-1/LTC3722-2 Dual Mode Phase Modulated Full-Bridge Controllers
LT3804
Secondary Side Dual Output Controller with Opto Driver
Regulates Two Secondary Outputs; Optocoupler Feedback Driver and
Second Output Synchronous Driver Controller
LTC3901
Secondary Side Synchronous Driver for Push-Pull
and Full Bridge Converters
Fault Timer, Reverse Current Sense, SO8
LTC3723-1/LTC3723-2 Synchronous Push-Pull Controllers
Highest Efficiency Push-Pull Controllers
LTC4440
100V High Side MOSFET Driver
SOT-23 and MSOP; 1.6Ω Pull-Down, 2.4A Pull-Up
sn37211 37211fs
LT/TP 0504 1K • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
16
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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